Micron Announces Breakthrough In Flash Memory Endurance

Micron’s new MLC Enterprise NAND device achieves 30 thousand write cycles – a 6x increase in endurance when compared to standard MLC NAND, according to the company. For enterprise applications that are more performance driven, Micron today also introduced a 34nm SLC Enterprise NAND device that achieves 300 thousand write cycles – a 3x increase in endurance when compared to standard SLC NAND.

These are good news indeed. It was already bad enough that MLC was typically only capable of enduring 10k erase cycles, the most recent Flash memory had dropped that value to half of that: 5k.

Increasing the endurance of MLC Flash to 30k erase cycles will allow for a much increased reliability without the need to resort to expensive SLC Flash, something that has been relegated to drives like the Intel X25-E or the OCZ Vertex-EX. This is also an important enchancement that will allow better chances of 3-bit per cell MLC NAND to be used in SSDs and devices that require more resilience than your typical thumb drive or portable media player.

Micron has a partnership with Intel to produce NAND Flash, so it's likely that this technology will soon make it's way to the highly awarded X25-M drives and others like the cheaper OCZ Agility - which, among other brands, also make use of Intel made NAND chips.

Source: Xbitlabs

AMD's Upcoming Phenom II X2 555 BE Overclocked to 6.6GHz

Complete with Youtube video of the feat, which was made possible with the help of some liquid nitrogen(LN2). 6.6GHz, unlocked to quad-core.

The AMD Phenom II X2 555 Black Edition is the successor to the well known Phenom II X2 550, which has made its rounds through the online media a while ago, due to the ability that some samples have of being unlocked to a full Phenom II X4.

This new X2 555 model is available in the AM3 form factor - which also works in AM2+ compatible motherboards - and has a clock of 3.2GHz, 6MiB of L2 cache and an HT link @ 4 GHz. Being a Black Edition CPU, it comes with no cooling fan and an unlocked multiplier.

This overclock was achieved on a Biostar TA785GE 128M motherboard, full with the unlocking to a Phenom II X4.
Biostar has been building some of the best overclocking motherboards out there and the rumor mill whispers that this is because the legendary Oskar Wu has moved there when he departed DFI.
Below, the video of windows booting. Notice that the CPU is based on the new C3 revision of the Phenom II core:

Source: XtremeSystems

AMD PRs Counter Paper Launch With Slides

Marketing slides, from AMD to Nvidia, with too little love in between. These are excerpts, the most interesting ones, so let's start by the end. It's the most important slide, left to be completely disregarded in a stack of more than twenty. It shouldn't be, since it sheds much light to what follows below. Remember: "may contain technical innacuracies".


Yup, all valid points. That Fermi was built for HPC, you already knew. You overshot on the die size yourselves but Nvidia is in worst shape.


What??? AMD's PRs don't have engineers they can talk to? They don't now how much bandwidth Fermi will have? Here's a hint: 4.8GHz GDDR5 on a 384bit bus equals 230GB/s.
2.72 TFLOPs/s? Yeah right, like if the card wouldn't blow up with such efficient codes... Where's the FireStream card that can really do that?
I already mentioned that AMD was marketing this card like Intel with the Pentium 4. The worse is we must gobble it up because it's still the fastest card around.

Predicting just 1.5TFLOPs/s for Fermi is harsh. The GT200 can manage 900+GFLOPs/s, the cores have more than doubled and the FMA instruction helps out in some situations. It may turn out to be also more than 2TFLOPs/s but, as with the AMD card, it will hardly be achievable in real world scenarios(although not by PWM capping reasons!).

The Radeon 5870 doesn't have 1600 shader cores, get over it, that's PR talk. It has 320 cores, where each is a 5 way vector unit. It's not the same thing. Neither are Nvidia's cores, which are groups of 32 cores performing the same instruction on different data offsets. It's not ideal, but it's still more efficient than vector units. We also don't see the 6.67x difference in "shader cores" versus the GeForce GTX 285 translated into performance gains that big and we won't when Fermi debuts. Bandwidth also plays a role, there's too much wasted transistors into too many shader cores per bandwidth.


The global data share seems a requirement for AMD's architecture due to the split nature of the L2 caches, which are tied to the memory controller. Nvidia has one of 768KiB, AMD has four of 128KiB each(old slide):


Coherency issues? Apparently, the AMD only Global data share solves that. I wouldn't say that's a victory. They're making too much of a fuss about something that, rightfully so, is not targeted at compute. The Radeon 5000 is targeted at gaming. End of story. If they don't care for the market, it would be wise to stop spreading FUD.


Nvidia shows "L2 cache (per SM)", which is an error, it's global, unique. The L1 is interchangeable with the shared memory in size, which is great.


All valid points. AMD can't touch Fermi for HPC applications, no problem there.


AMD must stop skewing the compute power. They are the first to market with a good card - it's not a great card but it's not terrible either. It's not up to HD 4800 standards but they still have a full three months to fix the lack of bandwidth before Nvidia releases anything Fermi related. By the time they do, they yields should be pretty good on the 5800 series and the dual GPU 5800 is shaping up to rule the high-end. And the high-end replacement should be around. Hardly will it have an increase bus width but GDDR5 can reach around 7GHz - if the memory controller allows it - which translates to 224GB/s.
Desperate moves for a company that's having trouble supplying enough 5800 cards to the customers.

Source: PCGH